One fundamental problem of charge transfer devices and specifically of charge coupled devices is that the charge transfer efficiency of these devices is limited. As a result, charge packets originally introduced into these devices dissipate in amplitude and diffuse in definition during transfer in the device, which may cause information represented by each charge packet to be lost before it can be retrieved. One prior art solution to limited charge transfer efficiency in charge coupled devices used in digital signal processing is to provide a binary charge refresher which accomplishes charge refreshment by comparing the dissipated signal charge packet with a reference. A resettable bistable multivibrator performs the comparison by latching into one of its two states depending upon whether the signal or reference is greater. The reference is selected to define a charge level which is above the charge coupled device fat zero. In one state, the multivibrator output fills a complete bucket in a charge coupled device output register to provide a logic "1" and in its other state leaves an empty bucket in the output register to provide a logic "0."
One problem with this type of prior art charge refreshment is that the feedback nodes of the multivibrator are typically connected to a large output capacitance, which limits the output voltage of the refresher, a problem which may be overcome by amplification of the signal and reference inputs to the multivibrator. However, it has been found that amplification of the inputs to the multivibrator by source followers can lead to a large offset voltage in the comparison function of the device, which, for many applications, is unacceptable.
Another problem of the prior art is that, in current efforts to develop charge coupled device (CCD) logic circuits, implementation of decoders and encoders requires that the output from a single device must fan out in a logic tree, a configuration well known to those skilled in the art. While logic fan-out has not presented a severe problem to logic designers using bipolar or MOSFET technology, logic fan-out in CCD logic circuits requires that an output charge packet be distributed over a large number of devices, which may lead to the dissipation of a single charge packet below the minimum signal level. The prior art solution to this problem has been to provide charge amplification using active devices which increase the power consumption of the CCD logic circuit, a significant disadvantage.